/*
 *  armboot - Startup Code for ARM926EJS CPU-core
 *
 *  Copyright (c) 2003  Texas Instruments
 *
 *  ----- Adapted for OMAP1610 OMAP730 from ARM925t code ------
 *
 *  Copyright (c) 2001	Marius Gr?ger <mag@sysgo.de>
 *  Copyright (c) 2002	Alex Z?pke <azu@sysgo.de>
 *  Copyright (c) 2002	Gary Jennejohn <garyj@denx.de>
 *  Copyright (c) 2003	Richard Woodruff <r-woodruff2@ti.com>
 *  Copyright (c) 2003	Kshitij <kshitij@ti.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */


#include <config.h>
#include <version.h>

/*
 *************************************************************************
 *
 * Jump vector table as in table 3.1 in [1]
 *
 *************************************************************************
 */


.globl _start
_start: b	reset
	ldr     pc, _undefined_instruction
	ldr     pc, _software_interrupt
	ldr     pc, _prefetch_abort
	ldr     pc, _data_abort
	ldr     pc, _not_used
	ldr     pc, _irq
	ldr     pc, _fiq

_undefined_instruction:	.word undefined_instruction
_software_interrupt:	.word software_interrupt
_prefetch_abort:	.word prefetch_abort
_data_abort:		.word data_abort
_not_used:		.word not_used
_irq:			.word irq
_fiq:			.word fiq
_pad:			.word 0x12345678 /* now 16*4=64 */

__blank_zone_start:
.fill 1024*4,1,0
__blank_zone_end:

.globl _blank_zone_start
_blank_zone_start:
.word __blank_zone_start


.globl _blank_zone_end
_blank_zone_end:
.word __blank_zone_end

	.balignl 16,0xdeadbeef
/*
 *************************************************************************
 *
 * Startup Code (reset vector)
 *
 * do important init only if we don't start from memory!
 * setup Memory and board specific bits prior to relocation.
 * relocate armboot to ram
 * setup stack
 *
 *************************************************************************
 */

_TEXT_BASE:
	.word	TEXT_BASE

.globl _armboot_start
_armboot_start:
	.word _start

/*
 * These are defined in the board-specific linker script.
 */
.globl _bss_start
_bss_start:
	.word __bss_start

.globl _bss_end
_bss_end:
	.word _end

#ifdef CONFIG_USE_IRQ
/* IRQ stack memory (calculated at run-time) */
.globl IRQ_STACK_START
IRQ_STACK_START:
	.word	0x0badc0de

/* IRQ stack memory (calculated at run-time) */
.globl FIQ_STACK_START
FIQ_STACK_START:
	.word 0x0badc0de
#endif


_clr_remap_spi_entry:
    .word   SF_TEXT_ADRS + do_clr_remap - TEXT_BASE
_clr_remap_nand_entry:
    .word   NAND_TEXT_ADRS + do_clr_remap - TEXT_BASE

/*
 * the actual reset code
 */

reset:
	/*
	 * set the cpu to SVC32 mode
	 */
	mrs	r0,cpsr
	bic	r0,r0,#0x1f
	orr	r0,r0,#0xd3
	msr	cpsr,r0

	/*
	 * we do sys-critical inits only at reboot,
	 * not when booting from ram!
	 */

	/*
	 * flush v4 I/D caches
	 */
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */

	/*
	 * disable MMU stuff and caches
	 */
	mrc	p15, 0, r0, c1, c0, 0
	bic	r0, r0, #0x00002300	/* clear bits 13, 9:8 (--V- --RS) */
	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
	orr	r0, r0, #0x00000002	/* set bit 2 (A) Align */
	mcr	p15, 0, r0, c1, c0, 0

	mov 	r0, pc, lsr#24
	cmp 	r0, #0x0
	bne	do_clr_remap

check_start_mode:
	ldr	r0, =REG_BASE_SCTL
	ldr	r0, [r0, #REG_SYSSTAT]
	mov	r6, r0, lsr#5
	and	r6, #0x1

	/* reg[0x2005008c:5]:
	 * 0:	start from spi
	 * 1:	start from nand
	 */

	cmp	r6, #BOOT_FROM_SPI
	ldreq   pc, _clr_remap_spi_entry

	ldr	pc, _clr_remap_nand_entry
	@b	.	/* bug here */

do_clr_remap:
	ldr     r4, =REG_BASE_SCTL
	ldr 	r0, [r4, #REG_SC_CTRL]

	/* reg[0x20050000:8]:
	 * 0:	keep remap
	 * 1:	clear remap
	 */
	@Set clear remap bit.
	orr 	r0, #(1<<8)
	str 	r0, [r4, #REG_SC_CTRL]

	@Setup TCM (ENABLED, 2KB)
	ldr     r0, =( 1 | (MEM_CONF_ITCM_SIZE<<2) | MEM_BASE_ITCM)
	mcr     p15, 0, r0, c9, c1, 1

	@enable I-Cache now
	mrc	p15, 0, r0, c1, c0, 0
	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
	mcr	p15, 0, r0, c1, c0, 0

	@Check if I'm running in ddr
	mov r0, pc, lsr#28
	cmp r0, #8
	bleq    relocate

	ldr     r0, _blank_zone_start
	ldr     r1, _TEXT_BASE
	sub     r0, r0, r1
	adrl    r1, _start
	add     r0, r0, r1
	mov     r1, #0          /* flags: 0->normal 1->pm */
	bl      init_registers

#ifdef  CONFIG_SVB_ENABLE
	bl	svb_voltage_adjust
#endif	/* CONFIG_SVB_ENABLE */

#ifndef CONFIG_SKIP_RELOCATE_UBOOT
relocate:
	@copy arm exception table in 0 address
	adrl	r0, _start
	mov	r1, #0
	mov	r2, #0x100		/* copy arm Exception table to 0 addr */
	add     r2, r0, r2
copy_exception_table:
	ldmia   r0!, {r3 - r10}
	stmia   r1!, {r3 - r10}
	cmp     r0, r2
	ble     copy_exception_table

	@relocate U-Boot to RAM
	adrl	r0, _start		/* r0 <- current position of code   */
	ldr	r1, _TEXT_BASE		/* test if we run from flash or RAM */
	cmp     r0, r1                  /* don't reloc during debug         */
	beq     stack_setup
	ldr	r2, _armboot_start
	ldr	r3, _bss_start
	sub	r2, r3, r2		/* r2 <- size of armboot            */
	add	r2, r0, r2		/* r2 <- source end address         */

copy_loop:
	ldmia	r0!, {r3-r10}		/* copy from source address [r0]    */
	stmia	r1!, {r3-r10}		/* copy to   target address [r1]    */
	cmp	r0, r2			/* until source end addreee [r2]    */
	ble	copy_loop
#endif	/* CONFIG_SKIP_RELOCATE_UBOOT */

	/* Set up the stack						    */
stack_setup:
	ldr	r0, _TEXT_BASE		/* upper 128 KiB: relocated uboot   */
	sub	r0, r0, #CONFIG_SYS_MALLOC_LEN	/* malloc area		    */
	sub	r0, r0, #CONFIG_SYS_GBL_DATA_SIZE /* bdinfo		    */
#ifdef CONFIG_USE_IRQ
	sub	r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ)
#endif
	sub	sp, r0, #12		/* leave 3 words for abort-stack    */
	bic	sp, sp, #7		/*8-byte alignment for ABI compliance*/

clear_bss:
	ldr	r0, _bss_start		/* find start of bss segment        */
	ldr	r1, _bss_end		/* stop here                        */
	mov	r2, #0x00000000		/* clear                            */

clbss_l:str	r2, [r0]		/* clear loop...                    */
	add	r0, r0, #4
	cmp	r0, r1
	ble	clbss_l

	ldr	pc, _start_armboot

_start_armboot:
	.word start_armboot

/*
 *************************************************************************
 * SVB Voltage Adjust
 *************************************************************************
 */
svb_voltage_adjust:
	mov r6, lr

	@ PWM clock enable
	ldr r3, =CRG_REG_BASE
	mov r2, #0x2
	str r2, [r3, #0x38]

	@ set core voltage as 1V2(pwm freq 60kHz,mark-space ratio 40%)
	ldr r3, =MEM_BASE_ITCM
	ldr r0, [r3, #PWM_FREQ_OFFSET]
	ldr r1, [r3, #SPACE_RARIO_DEFAULT]
	bl set_pwm_voltage

	@ wait for pwm output stable(100ms is recommended).
	ldr r0, =0x2aaaaa
	bl svb_time_delay

	mov r5, #0x0			/* clear */
	mov r4, #0x0			/* clear */
	ldr r3, =CRG_REG_BASE

read_speed_monitor:
	@ read speed counter for 8 times
	mov r1, #0x3
	str r1, [r3, #0xf4]		/* 0x3 --> 0x200300f4 */

	mov r2, #0x7
	str r2, [r3, #0xf4]		/* 0x7 --> 0x200300f4 */
do_read_speed:
	ldr r2, [r3, #0xf8]		/* r2  <-- 0x200300f8 */

	mov r1, r2, lsr#9
	and r1, #0x1
	cmp r1, #0x0
	beq do_read_speed		/* invalid, read again */
	ldr r1, =0x1ff
	and r2, r2, r1
	add r4, r4, r2			/* r4 += corner_read */
	add r5, r5, #0x1
	cmp r5, #8			/* try at least 8 times */
	bne read_speed_monitor

	mov r2, r4, lsr#0x3		/* get average: r2 = r4/8 */

	@ r2 = value of SpeedMonitor

	ldr r3, =MEM_BASE_ITCM
get_corner_type:
	ldr r1, [r3, #MAX_CORNER_AA]
	cmp r1, r2
	bgt set_aa_pwm
	ldr r1, [r3, #MAX_CORNER_BB]
	cmp r1, r2
	bgt set_bb_pwm
	b set_cc_pwm
set_aa_pwm:
	ldr r1, [r3, #SPACE_RATIO_AA]
	b do_pwm_set
set_bb_pwm:
	ldr r1, [r3, #SPACE_RATIO_BB]
	b do_pwm_set
set_cc_pwm:
	ldr r1, [r3, #SPACE_RATIO_CC]
do_pwm_set:
	@ hi3518 has 3 PWM outputs, and PWM2 is used here
	ldr r3, =MEM_BASE_ITCM
	ldr r0, [r3, #PWM_FREQ_OFFSET]	/* get pwm frequency */
	bl set_pwm_voltage

	@ wait for pwm voltage becoming stable.
	ldr r0, =0x2aaaaa
	bl svb_time_delay

pwm_ddr_training:
	ldr r3, =DDRC_REG_BASE
	ldr r1, =0x32409000
	str r1, [r3, #0x58]

	ldr r3, =DDR_PHY_BASE
	ldr r1, =0x01842202
	str r1, [r3, #0x408]

	ldr r1, =0x81
	str r1, [r3, #0x404]

	@ a delay here
	mov r0, #0x500
	bl svb_time_delay

ddr_training_read:
	ldr r1, [r3, #0x40c]
	and r1, #0x1
	cmp r1, #0x1
	bne ddr_training_read

	ldr r1, =0x01842200
	str r1, [r3, #0x408]

	ldr r3, =DDRC_REG_BASE
	ldr r1, =0x32409062
	str r1, [r3, #0x58]
	mov pc, r6

/*
 * func: svb_time_delay
 * r0: delay time
 */
svb_time_delay:
	sub r0, r0, #1
	cmp r0, #0
	bne svb_time_delay
	mov pc, lr

/*
 * func: set_pwm_voltage
 * r0: frequency;
 * r1: mark-space ratio
 */
set_pwm_voltage:
	ldr r3, =PWM_REG_BASE
	ldr r2, [r3, #0x4c]
	bic r2, #1
	str r2, [r3, #0x4c]		/* disable pwm2 output */

	ldr r2, [r3, #0x4c]
	orr r2, r2, #4			/* always output wave */
	bic r2, r2, #3			/* set normal rectangular wave output */
	str r2, [r3, #0x4c]

	str r0, [r3, #0x40]		/* set pwm frequency as 60khz */
	str r1, [r3, #0x44]		/* set pwm mark-space ratio as 40% */

	ldr r2, [r3, #0x4c]
	orr r2, r2, #1
	str r2, [r3, #0x4c]		/* enable pwm output */
	mov pc, lr


/*
 *************************************************************************
 *
 * CPU_init_critical registers
 *
 * setup important registers
 * setup memory timing
 *
 *************************************************************************
 */
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
cpu_init_crit:
	/*
	 * flush v4 I/D caches
	 */
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7, 0	/* flush v3/v4 cache */
	mcr	p15, 0, r0, c8, c7, 0	/* flush v4 TLB */

	/*
	 * disable MMU stuff and caches
	 */
	mrc	p15, 0, r0, c1, c0, 0
	bic	r0, r0, #0x00002300	/* clear bits 13, 9:8 (--V- --RS) */
	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
	orr	r0, r0, #0x00000002	/* set bit 2 (A) Align */
	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
	mcr	p15, 0, r0, c1, c0, 0

	/*
	 * Go setup Memory and board specific bits prior to relocation.
	 */
	mov	ip, lr		/* perserve link reg across call */
	@bl	lowlevel_init	/* go setup pll,mux,memory */
	mov	lr, ip		/* restore link */
	mov	pc, lr		/* back to my caller */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */

#ifndef CONFIG_PRELOADER
/*
 *************************************************************************
 *
 * Interrupt handling
 *
 *************************************************************************
 */

@
@ IRQ stack frame.
@
#define S_FRAME_SIZE	72

#define S_OLD_R0	68
#define S_PSR		64
#define S_PC		60
#define S_LR		56
#define S_SP		52

#define S_IP		48
#define S_FP		44
#define S_R10		40
#define S_R9		36
#define S_R8		32
#define S_R7		28
#define S_R6		24
#define S_R5		20
#define S_R4		16
#define S_R3		12
#define S_R2		8
#define S_R1		4
#define S_R0		0

#define MODE_SVC 0x13
#define I_BIT	 0x80

/*
 * use bad_save_user_regs for abort/prefetch/undef/swi ...
 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
 */

	.macro	bad_save_user_regs
	@ carve out a frame on current user stack
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}	@ Save user registers (now in svc mode) r0-r12

	ldr	r2, _armboot_start
	sub	r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
	@ set base 2 words into abort stack
	sub	r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8)
	@ get values for "aborted" pc and cpsr (into parm regs)
	ldmia	r2, {r2 - r3}
	add	r0, sp, #S_FRAME_SIZE		@ grab pointer to old stack
	add	r5, sp, #S_SP
	mov	r1, lr
	stmia	r5, {r0 - r3}	@ save sp_SVC, lr_SVC, pc, cpsr
	mov	r0, sp		@ save current stack into r0 (param register)
	.endm

	.macro	irq_save_user_regs
	sub	sp, sp, #S_FRAME_SIZE
	stmia	sp, {r0 - r12}			@ Calling r0-r12
	@ !!!! R8 NEEDS to be saved !!!! a reserved stack spot would be good.
	add	r8, sp, #S_PC
	stmdb	r8, {sp, lr}^		@ Calling SP, LR
	str	lr, [r8, #0]		@ Save calling PC
	mrs	r6, spsr
	str	r6, [r8, #4]		@ Save CPSR
	str	r0, [r8, #8]		@ Save OLD_R0
	mov	r0, sp
	.endm

	.macro	irq_restore_user_regs
	ldmia	sp, {r0 - lr}^			@ Calling r0 - lr
	mov	r0, r0
	ldr	lr, [sp, #S_PC]			@ Get PC
	add	sp, sp, #S_FRAME_SIZE
	subs	pc, lr, #4		@ return & move spsr_svc into cpsr
	.endm

	.macro get_bad_stack
	ldr	r13, _armboot_start		@ setup our mode stack
	sub	r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN)
	@ reserved a couple spots in abort stack
	sub	r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8)

	str	lr, [r13]	@ save caller lr in position 0 of saved stack
	mrs	lr, spsr	@ get the spsr
	str	lr, [r13, #4]	@ save spsr in position 1 of saved stack
	mov	r13, #MODE_SVC	@ prepare SVC-Mode
	@ msr	spsr_c, r13
	msr	spsr, r13	@ switch modes, make sure moves will execute
	mov	lr, pc		@ capture return pc
	movs	pc, lr		@ jump to next instruction & switch modes.
	.endm

	.macro get_irq_stack			@ setup IRQ stack
	ldr	sp, IRQ_STACK_START
	.endm

	.macro get_fiq_stack			@ setup FIQ stack
	ldr	sp, FIQ_STACK_START
	.endm
#endif	/* CONFIG_PRELOADER */

/*
 * exception handlers
 */
#ifdef CONFIG_PRELOADER
	.align	5
do_hang:
	ldr	sp, _TEXT_BASE			/* switch to abort stack */
1:
	bl	1b				/* hang and never return */
#else	/* !CONFIG_PRELOADER */
	.align  5
undefined_instruction:
	get_bad_stack
	bad_save_user_regs
	bl	do_undefined_instruction

	.align	5
software_interrupt:
	get_bad_stack
	bad_save_user_regs
	bl	do_software_interrupt

	.align	5
prefetch_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_prefetch_abort

	.align	5
data_abort:
	get_bad_stack
	bad_save_user_regs
	bl	do_data_abort

	.align	5
not_used:
	get_bad_stack
	bad_save_user_regs
	bl	do_not_used

#ifdef CONFIG_USE_IRQ

	.align	5
irq:
	get_irq_stack
	irq_save_user_regs
	bl	do_irq
	irq_restore_user_regs

	.align	5
fiq:
	get_fiq_stack
	/* someone ought to write a more effiction fiq_save_user_regs */
	irq_save_user_regs
	bl	do_fiq
	irq_restore_user_regs

#else

	.align	5
irq:
	get_bad_stack
	bad_save_user_regs
	bl	do_irq

	.align	5
fiq:
	get_bad_stack
	bad_save_user_regs
	bl	do_fiq

#endif
#endif	/* CONFIG_PRELOADER */
#include "lowlevel_init.S"
